Emerging memory architectures are designed to handle a range of different request sizes and may include memories with different characteristics. For example, there have been several proposals for memory composed of dynamic random-access memory (DRAM) and phase-change memory (PCM) or multiple types of DRAM chips (e.g. double data rate (DDR), low power DDR (LPDDR), reduced-latency DRAM (RLDRAM)). Furthermore, some computer systems may support non-uniform memory access (NUMA), where information is placed according to the performance of available memory. Memories can also have their characteristics altered dynamically, even when composed of the same types of memories e.g. NAND flash memory. For example, multi-channel memories and dynamic DRAM frequency switching alter the characteristics of the memory. Non-volatile memory characteristics can also be highly non-uniform, where certain NAND flash pages are faster to read or write than others, with latencies changing as they wear out, or with different levels of multi-level-cells (MLC) within or between different flash memories.
Other examples of dynamic memory re-configuration include dynamic placement of information in a computer system on memories with different fixed or configurable characteristics. For example, requests from highly serial or write-dominated algorithms can be directed towards high-latency volatile memories, while requests from parallel algorithms can be served from lower latency or non-volatile memories. In other examples, requests from highly serial or write-dominated algorithms may also be directed towards low-latency memories, while requests from parallel algorithms may be served from higher-latency. Selection a memory allocation of information related to an algorithm based on characteristics of the algorithm may enable an effective cost-performance-energy trade-off in the memory system design.
Conventional proposals for control and coordination of these disparate adaptive mechanisms is to incorporate memory management as part of standard operating system software, with access to a limited set of accessible hardware performance counters to guide memory configuration decisions. With the move towards abstracted memory and hardware, which offloads memory control to the memory itself, standardized software interfaces will be insufficient. In particular, abstracted memories are capable of exploiting memory variations and self-tuning to maximize performance, while current software is unaware of these capabilities. The memory control system benefits from knowledge of host processor state, but there exists no mechanism to feed the memory control logic with appropriate statistics.